Computer systems often include a display device, such as a cathode ray tube (CRT) or a liquid crystal display which provides a display of information generated by the computer and which also displays a cursor with the other information on the display device. Often, this display device is a raster scanned device such as a video CRT, and the cursor is generated on the screen on the display device in a line by line manner as with the other information which is displayed on the device. It will be appreciated that the cursor is used by the user to indicate some operation to the computer and also tells the user the position at which a data input may occur. FIG. 5 shows a typical cursor of the prior art which is labeled as cursor 203. As is well know, a user may control the movement of the cursor 203 by an input device, such as a mouse, to cause the pointer to appear over an object which is also displayed on the screen in order to select that object or to insert text at the location indicated by the cursor, etc.
FIG. 1 shows a typical prior art implementation of an apparatus which generates the cursor for display on a computer controlled display device. It will be appreciated that the frame buffer 10 contains the information in digital form which is to be displayed in a bit-mapped manner onto the display device. Bus 16 provides the digitized display data through the multiplexor 12 and the bus 22 to a digital to analog (D/A) converter. The D/A converter is coupled to the display device to provide the analog values of the bit mapped image to the display device in the well known manner of the prior art. Typically, most of the screen area of the display device will be occupied by information obtained from the frame buffer 10, and very little of that screen space will be taken up by the cursor which is positioned at some point on the screen of the display device.
The digitized image of the cursor is stored in the memory 11 which is often a static random access memory (SRAM) which is addressed by the address counter 15 via the address and control bus 18 so that the cursor memory 11 provides an output of the value of the cursor's digitized image at the particular addressed location over line 21 to the multiplexor 12. The NOR gate 19 is coupled to receive the output values from the cursor memory 11 and it determines, via its output which is coupled to the select line 20 of the multiplexor 12, whether the value of the cursor or the value of the frame buffer at the particular pixel location of the display device will be sent through the multiplexor 12 to the D/A converter and ultimately to the display device. Thus, the NOR gate 19 and the select line 20 will select between information in the frame buffer 10 or information in the cursor memory 11 depending on whether a zero or a one is present on line 21. It will be appreciated that whenever the value of the cursor is zero (e.g. no color) then the values from the frame buffer at that particular pixel will be selected by the multiplexor 12 for display on the display device.
The controller 14 provides for the control of the cursor memory 11 through the address counter 15. The controller 14 generates the appropriate signals to cause the address counter to count sequentially through locations in the cursor memory 11 to provide a sequential output of the cursor data from the cursor memory 11. Each line of the cursor data represents a portion of the raster scanned line which is currently being read out from the frame buffer 10. The cursor memory will often provide a limited amount of storage; for example, a typical cursor size is 32 pixels by 32 pixels. The controller 14 receives an input indicating the starting X (Xs) and the starting Y (Ys) position of the cursor, which position typically indicates the upper left land corner of the block area (usually rectangular) of the cursor, such as the upper left hand corner of the cursor block 202 shown in FIG. 5. It will be appreciated that there are many ways well known in the prior art which can provide this starting position, such as techniques for determining the position of a cursor control device such as a mouse. The controller 14 typically also includes an input for the vertical length (YI) of the cursor block such as the vertical length in FIG. 5 shown between dashed lines 206 and 207. The controller 14 also includes inputs for receiving the pixel clock which is the clock which controls the rate at which pixels are displayed and refreshed on the display device in the normal raster scanned manner. Furthermore, the controller 14 includes an input to receive the horizontal and the vertical retrace signals which are provided in the normal fashion by the video control circuitry in order to create a typical raster scanned image on a display device.
Prior art cursor generating apparatuses, while providing an effective means for displaying cursors in typical computer systems, do not provide a high enough throughput in faster computer systems where the pixel clock is operated at very high frequencies. In these circumstances, depending on the rate of the pixel clock, it is often possible to improve the speed of these cursor generators by using faster memory integrated circuits for the cursor memory 11, such as very fast static RAM. However, these memories are often still not fast enough to achieve a proper sequential output from the memory at very pixel clock rates.
Consequently, it is an object of the present invention to provide an improved apparatus for generating a cursor at a high speed for a high speed computer display system, particularly where the pixel clock is operating at a very high rate. These high pixel rates are often mandated by the size of larger screens on display devices which require that, in order to prevent the flickering of the displayed image to which the eye is so sensitive, the pixel clock be accelerated in order to draw the entire image in the typical raster scan manner on the screen at least 30 frames per second. It is a further object of the present invention to provide a sophisticated embodiment for a cursor generator in those circumstances where typical CMOS integrated circuits are too slow to keep up with very high pixel clock rates.